1. Field of the Invention
This invention relates to a memory array and byte-alterable support circuits and methods for writeable memory technologies.
More particularly this invention relates to providing a memory array and support which allow byte access for programming, erasing and reading.
2. Description of Related Art
Memory cells which can be programmed and erased and re-programmed are known as Electrically, Erasable Programmable Read Only Memory, EEPROM. In the prior art, there are known types of memory arrays and peripheral circuits which are used with EEPROM, flash memory, or non-volatile memory. The main deficiencies of the prior art are the inability to access the memory arrays on a byte basis for programming, erasing and reading the memory arrays. Another deficiency of the prior art is the large amount of voltage stress required to program and erase the memory cells of the array.
In the prior art versions of split-gate memory cells, SST, it was difficult to implement byte-alterable functions. The SST memory cell did not have byte access capability, since word lines were shared by to many memory cells. In addition, the SST memory cell had two adjacent rows share a source line during programming. This required that these shared or adjacent rows be erased at the same time or else disturb the cells sharing the source line.
U.S. Pat. No. 5,812,452 (Hoang) “Electrically Byte-Selectable and Byte-Alterable Memory Arrays” describes a memory array which utilizes a byte (block) select transistor to allow the memory cells to be accessed and altered on a byte basis.
U.S. Pat. No. 6,201,732 B1 (Caywood) “Low Voltage Single CMOS Electrically Erasable Read-Only Memory” describes a CMOS memory cell which can can be programmed, erased and operate at low voltages.
U.S. Pat. No. 6,128,220 (Banyai et al.) “Apparatus for Enabling EEPROM Functionality Using a Flash Memory Device” discloses a byte-alterable non-volatile memory.
U.S. Pat. No. 6,088,269 (Lambertson) “Compact Page-Erasable EEPROM Non-Volatile Memory” discloses a page erasable memory which uses two layers of conductive or semiconductive material.
U.S. Pat. No. 6,212,102 (Georgakos et al.) “EEPROM and Method for Triggering the EEPROM” discloses a programmable memory which uses source side selection. This source side selection allows the EEPROM to be protected against unintended loss of data stored in it.